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Friday, 5 June 2015

Computer Architecture -Model question paper for B.E/B.Tech Engineering


1(a) Represent the decimal number -4321 as packed decimal format (in hex) and unpacked decimal format (in hex). (6 Marks)
(b) Compute the area in rbe with and without aspect-mismatch adjustment of a 32KB direct-mapped cache with 256-bit lines and a 20-bit tag. (8 Marks)
(c) Plot Sopt with respect to clock skew factor (k) for k = 0.05 to k = 0.20. Assume T=120 ns, C= 5 ns and b=0.2. (6 Marks)
2(a) What is control transfer? Explain the three types. (8 Marks)
(b) What does the difference between the branch target reference capture rates of a small forward branch table and a small backward branch table tells us about the nature of conditional branches? What high level language instructions would produce these distributions? (6 Marks)
(c) Assume for the R/M architecture that a conditional branch takes one cycle if the condition code was set prior to the preceding instruction, and two cycles otherwise. Assume all other instructions take a single cycle. What is the range of cycles per 100 HLL instructions for the scientific workload? What is the expected number of cycles? (6 Marks)
3(a) Write a note on the evaluation of pipelined processor performance. (6 Marks)
(b) Explain the terms branch speedup and branch elimination. (4 Marks)
(c) Describe I-buffer arrangements (number of in-line and target registers) suitable to each of the IBM 3033, Amdahl V-8 and MIPS R2000 timing templates and for w (the size of the IF path) = 4 and 8 bytes. Assume branch prediction is used. (10 Marks)
4(a) Caches work on the basis of the locality of program behavior. Explain. (4 Marks)
(b) Write a note on strategies for line replacement at miss time. (6 Marks)
(c) Explain instruction traffic, data read traffic and data write traffic. (6 Marks)
(d) For an 8KB integrated level 1 cache (direct mapped, 16 B lines) and a 128 KB integrated level 2 cache (2W set associative, 16 B lines) find the solo and local miss rate for the level 2 cache. (4 Marks)
5(a) Distinguish between Hellerman’s model and Strecker’s model. (6 Marks)
(b) Design a SECDED (Hamming type) coding scheme for a memory with data word size of 18 bits. Show placement of each check bit and give logic equations for its action. (8 Marks)
(c) A processor without a cache accesses evert t-th element of a k-element vector. Each element is one physical word. Assuming Ta=200ns, Tc=100ns, and Tbus=25 ns, plot the average access time per element for an 8-way, low-order interleaved memory for t=1 to 12 and k=100. (6 Marks)
6(a) Using a neat figure, explain the major data paths in a generic vector processor. (8 Marks)
(b) What are interleaved caches? (4 Marks)
(c) Suppose we want to use m = 5 memory modules. Find the module addess and the address within the module for the following (hex) addresses:
(a) F37B90      (b) AA3347                                                                             (4 Marks)
(d) A certain vector processor has a memory buffer that does not allow reconfiguration (each TBF/m is a separate buffer). How does this affect the overall overflow probability? (4 Marks)
7(a) What is scheduling? Write a detailed note on run-time scheduling techniques. (8 Marks)
(b) Explain directory-based protocols. (4 Marks)
(c) Links are characterized in three ways. Explain. (4 Marks)
(d) Discuss the relative advantages of update and invalidate protocols for multi-node switched shared memory multiprocessors. (4 Marks)
8(a) Write a note on redundancy in disk arrays. (6 Marks)
(b) Distinguish between pipeline timing analysis and pipeline penalty analysis. (8 Marks)
(C) A RAID storage system is to be implemented with 16 drives. These drives can  be configured independently, striped or synchronized. Configure a RAID-1, RAID-2 and RAID-5 storage system that maximizes the amount of data storage. What fraction of storage is devoted to data for each configuration? (6 Marks)


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